Systems which use microprocessor chips to execute instructions received from a memory are already well known. In such systems, the memory and a microprocessor chip are normally connected by printed circuits which facilitate the flow of instructions and data from the memory to the chip and the flow of processed data back to the memory.
Peripheral computer components such as disks, keyboards and monitors are normally also connected to the system in order to load and initiate the execution of instructions and to store and to monitor the results of such execution.
Instructions and data are usually read into main memory from a disk so that they may be executed in a programmed sequence. That is to say, the memory will provide the microprocessor with instructions to be executed and the data to be processed. The microprocessor processes the data as instructed by the instructions in the main memory instruction by instruction until the end of the programmed sequence is reached.
It has been a major effort throughout the computer industry to provide smaller and smaller computers which are capable of performing the same functions as large main frame computers. Large main frame computers are provided with central processing units for executing all of the set of instructions in the memory. Smaller computers, i.e. "micro-computers," use microprocessor chips instead of central processing units. However, it has not been technically possible and economically feasible to build a microprocessor chip which will execute all of the set of instructions normally found in the memory of large main frame computers.
However, it is possible to build a microprocessor chip capable of executing only a specific subset of the set of instructions in the memory. One useful method of virtually increasing the subset of instructions the microprocessor chip is capable of executing so that it is co-extensive with the set of instructions in the memory is the use of a co-microprocessor chip working in combination with a control storage portion of the memory.
Whenever the microprocessor chip is directed to execute a main frame instruction which is not a part of the specific subset of instructions it performs, the microprocessor chip turns itself off and turns on the co-microprocessor chip. The co-microprocessor chip has its own instructions in the control storage to emulate the execution of the main frame instruction. The co-microprocessor chip and the control storage work in such a way that the activity of the co-microprocessor chip is transparent to the program in the main storage portion of the memory.
For example, if the main frame instruction which is not a part of the specific subset is an invalid instruction, it will be recognized as such by the microprocessor. The co-microprocessor will be activated by the microprocessor and will execute its own program from control storage. This program in control storage can instruct the co-microprocessor chip to read the main frame instruction from main storage. Next the co-microprocessor compares the instruction in question with the set of main frame instructions that it emulates. The results of the comparison will show that the main frame instruction is invalid. The co-microprocessor will then emulate the action that would happen on a main frame computer when an invalid instruction is encountered. The co-microprocessor then returns control to the microprocessor which in turn continues processing main frame instructions. The above emulated action normally causes the main frame to invoke an instruction sequence that usually results in an error message being displayed on a monitor.
If the instruction which is not a part of the specific subset of instructions is a valid instruction from the set of instructions, it will be emulated by the co-microprocessor. That is, the co-microprocessor will compare the instruction with the set of instructions, as described above, to determine that it is a valid main frame instruction. The co-microprocessor chip then reads the data to be operated on from the main storage and processes it according to the main frame instructions architecture, after which the results of the operation will be written into main storage. Again, the co-microprocessor returns control to the microprocessor which in turn continues processing the next main frame instruction.
The small co-microprocessor chip system has worked well in enabling the emulation of larger main frame computers. However, the need to make even smaller, faster, more reliable systems which consume less power and require less cooling while still being capable of executing the full set of instructions of a main frame computer has highlighted the co-microprocessor system as an area where even further improvements are desirable.
The co-microprocessor chip takes up space on a printed circuit board in the computer, it requires power and produces heat, all of which are not desirable attributes. Further, the fact that the co-microprocessor chip is executing instructions from control storage while working on data from main storage means that it must issue read/write steering cycles much more often than the microprocessor chip which is working with instructions and data both in the same storage. Although each cycle requires only a short time, the great number of such additional cycles required for such co-microprocessing result in perceptibly slower execution of instructions in a computer.
In prior art data processing systems using co-microprocessors, the microcode instructions in the control storage for use in emulation often must be written in a different language than the directly executed instructions in the main storage. The development of improved co-microprocessors often means that new microcode instructions must be written for the control storage emulation programs at considerable expense and effort. It would be desirable to produce a data processing system with directly executed instructions in main storage and microcode instructions in control storage memories having the same language.